TMS32020 datasheet(28/57 Pages) TI

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2–14

FSR

FSX

Secondary

Primary

Secondary

Primary

Secondary

Primary

Transmit

Conversion

Preload A

Transmit

Conversion

Preload B

Transmit

Conversion

Preload C

Receive

Conversion

Period A

Receive

Conversion

Period B

Figure 2–7. More Than One Set of Primary and Secondary DX

Serial Communications Between Two Receive Frame Syncs

2.24 System Frequency Response Correction

The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board

second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be

inserted into or omitted from the signal path by digital-signal-processor control (data bit D9 in the DX

secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor

low-pass filter. When the TB register (see Figure 2–1) equals 15, the correction results of Figures 5 – 5, 5 – 6,

and 5 –7 can be obtained.

The (sin x)/x correction [see section (sin x)/x] can also be accomplished by disabling the on-board

second-order correction filter and performing the (sin x)/x correction in digital signal processor software. The

system frequency response can be corrected via DSP software to

± 0.1 dB accuracy to a band edge of

3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, that

requires seven TMS320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an

overhead factor of 1.1% and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (Sin x)/x

Correction Section for more details).

2.25 (Sin x)/x Correction

If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be

accomplished in digital signal processor (DSP) software. (Sin x)/x correction can be accomplished easily

and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band

edge of 3000 Hz by using a first-order digital correction filter. The results shown are typical of the numerical

correction accuracy that can be achieved for sample rates of interest. The filter requires seven instruction

cycles per sample on the TMS320 DS. With a 200-ns instruction cycle, nine instructions per sample

represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively.

This correction adds a slight amount of group delay at the upper edge of the 300-Hz to 3000-Hz band.

2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function

The (sin x)/x roll-off error for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz

for the various sampling rates is shown in Table 2–5 (see Figure 5 –7).

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