TLV320AD11A

3.3 V INTEGRATED ADSL OVER POTS CODEC

SLWS087B – JUNE 1999 – REVISED MARCH 2000

9

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

register programming (see Figure 6 for timing and format details)

Table 2. System Control Registers (SCR)

REGISTER

DEFAULT

NAME

ADDRESS

S3, S2, S1, S0

MODE

DEFAULT

VALUE

FUNCTION

SCR0

0000

R

00000000

SCR0

0000

W

D0: S/W RESET (self clearing)

SCR1

0001

R/W

00000000

D[4:0]=TX channel PAA gain select. D[4:0]=00000 for 0 dB

D[4:0]=11000 for –24 dB

SCR2

0010

R/W

00000000

D[5:0]=RX PGA2. D[5:0]=000000 for 0 dB. D[5:0]=101110 for 11.5 dB.

SCR3

0011

R/W

00000000

D[2:0]= RX EQ slope select. D[2:0]=000 for 0dB/MHz, D[2:0]=001 for 5 dB/MHz,

D[2:0]=101 for 25 dB/MHz

SCR4

0100

R/W

00000000

D[7:0]=VCXODAC (low 8 bits of 12-bit DAC code)

SCR5

0101

R/W

00000000

D[7:0]=VCXODAC (high 8 bits of 12-bit DAC code)

SCR6

0110

R/W

00000000

D[7:0]=GP[7:0]

SCR7

0111

R/W

00000000

MISC control (set to 1 to enable)

D0: bypass TX DHPF (25.875 kHz)

D1: S/W power-down RX channel

D2: S/W power-down TX channel

D3: analog loop-back (TX channel)

D4: digital loop-back (TX and EC channel)

D5: TX parallel interface (read-back) test mode enable

D6: EC channel power down

D7: EC analog loop-back

SCR8

1000

R/W

00000000

D[4:0]=EC channel PAA gain select. D[4:0]=00000 for 0 dB.

D[4:0]=11000 for –24 dB.

SCR9

1001

R/W

00000000

D[7:0]=RX offset low

SCR10

1010

R/W

00000000

D[7:0]=RX offset high

SCR11

1011

R/W

00000000

D[4:0]=TX digital gain select. The gain range is –1dB to 1dB in 0.1 dB-steps.

D[4:0]=00000 for 0 dB. D[4:0]=00001 for +0.1 dB. D[4:0]=01010 for +1 dB.

D[4:0]=10000 for –1 dB. D[4:0]=11001 for –0.1 dB.

SCR12

1100

R/W

00000000

D[2:0]=RX PGA1. D[2:0]=000 for 0 dB. D[2:0]=110 for 6 dB.

SCR13

1101

R/W

00000000

D[4:0]=EC digital gain select. The gain range is –1dB to 1dB in 0.1-dB steps.

D[4:0]=00000 for 0 dB. D[4:0]=00001 for +0.1 dB. D[4:0]=01010 for +1 dB.

D[4:0]=10000 for –1 dB. D[4:0]=11001 for –0.1 dB.

SCR14

1110

R/W

00000000

D0: Sync the write operation when ONE_WE is selected. After D0 is set to 1, the first

pulse of WETX goes to TX channel, and the second pulse goes to EC channel.

The bit will be self-cleared to 0.

D1: enable FIFO (first-in, first-out). See Note 1.

D2: Bypass EC DHPF (25.875 kHz)

D3: ECNULL. When D3 is set to 1, ECP and ECM are connected to weakly driven

mid supply. It can only be used during EC power-down mode.

NOTE 1: It is a two-stage FIFO buffer, and can store up to two write-samples if asynchronous write operation is required.

SCR0 – system control register

Address:0000b

Contents at reset: 00000000b

D7

D6

D5

D4

D3

D2

D1

D0

REGISTER

VALUE (HEX)

DESCRIPTION

0

0

0

0

0

0

0

1

01

S/W reset (self clearing). All control registers are set to reset content.