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TMS320VC5421 Datasheet(PDF) 61 Page - Texas Instruments |
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TMS320VC5421 Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 parallel I/O interface timing switching characteristics over recommended operating conditions for a parallel I/O port read (IOSTRB = 0)† (see Figure 28) PARAMETER MIN MAX UNIT td(CLKL-A) Delay time, CLKOUT low to address valid 0 4 ns td(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low 0 4 ns td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high 0 4 ns th(A)IOR Hold time, address after CLKOUT low 0 4 ns † Address and IS timings are included in timings referenced as address. timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 28) MIN MAX UNIT ta(A)IO Access time, read data access from address valid 5H–3 ns ta(ISTRBL)IO Access time, read data access from IOSTRB low 2H–3 ns tsu(D)IOR Setup time, read data before CLKOUT high 4 ns th(D)IOR Hold time, read data after CLKOUT high 0 ns th(ISTRBH-D)R Hold time, read data after IOSTRB high 0 ns † Address and IS timings are included in timings referenced as address. IS R/W IOSTRB PPD[15:0] PPA[18:0] CLKOUT th(A)IOR td(CLKH–ISTRBH) th(D)IOR tsu(D)IOR ta(A)IO td(CLKH–ISTRBL) td(CLKL–A) ta(ISTRBL)IO th(ISTRBH–D)R Figure 28. Parallel I/O Port Read (IOSTRB=0) |
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