June 2009

PCS1P2192A

rev 1.0

VDP Multiple Pixel Clock Generator

5 of 8

Notice: The information in this document is subject to change without notice.

Typical Application Schematic

PCB Layout Recommendation

For optimum device performance, following guidelines are recommended.

•

Dedicated VDD and GND planes.

•

The device must be isolated from system power supply noise. A 0.01µF decoupling capacitor should be

mounted on the component side of the board as close to the VDD pin as possible. No vias should be

used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via

should be kept as short as possible. All the VDD pins should have decoupling capacitors.

•

In an optimum layout all components are on the same side of the board, minimizing vias through other

signal layers.

A typical layout is shown in the figure

CLKIN

GND

CLKOUT

S2

S0

S1

1

2

3

4

5

7

8

REF 6

VDD

VDD

0Ω

0Ω

0Ω

0Ω

Use either pull-up or pull-down

0Ω Resistor with [S2:S0] for selection of

CLKOUT frequencies

VDD

0.01uF

GND

VDD

0Ω

CLKIN

0Ω

As short

as possible

GND

VDD