CDCE62002 datasheet(16/49 Pages) TI

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SPI CONTROL INTERFACE TIMING

SPI_CLK

Bit0

Bit1

Bit29

Bit30

Bit31

SPI_LE

SPI_MOSI

t 5

t 6

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

Bit 30

Bit 31

Bit 0

Bit 1

Bit 2

t 4

t 3

CDCE62002

SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Figure 12. Timing Diagram for SPI Write Command

Figure 13. Timing Diagram for SPI Read Command

Table 5. SPI Bus Timing Characteristics

SPI BUS TIMINGS

PARAMETER

MIN

TYP

MAX

UNIT

fClock

Clock Frequency for the SPI_CLK

MHz

SPI_LE to SPI_CLK setup time

SPI_MOSI to SPI_CLK setup time

SPI_MOSI to SPI_CLK hold time

SPI_CLK high duration

SPI_CLK low duration

SPI_CLK to SPI_LE Setup time

SPI_LE Pulse Width

SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE)

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