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TMP112AIDRLR Datasheet(PDF) 14 Page - Texas Instruments |
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TMP112AIDRLR Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 24 page ![]() TWO-WIRE TIMING DIAGRAMS SCL SDA t (LOW) t R t F t (HDSTA) t (HDSTA) t (HDDAT) t (BUF) t (SUDAT) t (HIGH) t (SUSTA) t (SUSTO) P S S P Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte Frame4DataByte2 1 StartBy Master ACKBy TMP112 ACKBy TMP112 ACKBy TMP112 StopBy Master 1 9 1 1 D7 D6 D5 D4 D3 D2 D1 D0 9 Frame3DataByte1 ACKBy TMP112 1 D7 SDA (Continued) SCL (Continued) D6 D5 D4 D3 D2 D1 D0 9 9 SDA SCL 0 0 1 0 A1 (1) A0 (1) R/W 0 0 0 0 0 0 P1 P0 ¼ ¼ NOTE:(1)ThevaluesofA0andA1aredeterminedbytheADD0pin. TMP112 SBOS473B – MARCH 2009 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Figure 15. Two-Wire Timing Diagram Figure 16. Two-Wire Timing Diagram for Write Word Format 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TMP112 |
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