LIS302DLH datasheet(25/37 Pages) STMICROELECTRONICS

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LIS302DLH

Doc ID 15797 Rev 1

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data in the low-power modes are computed with low-pass filter cut-off frequency defined by

DR1, DR0 bits.

DR bits, in the normal-mode operation, select the data rate at which acceleration samples

are produced. In low-power mode they define the output data resolution.

Table 20 shows all

the possible configuration for DR1 and DR0 bits.

7.3

CTRL_REG2 (21h)

Table 19.

Power mode and low-power output data rate configurations

PM2

PM1

PM0

Power mode selection

Output data rate [Hz]

ODRLP

Power-down

Normal mode

ODR

Low-power

0.5

Low-power

Table 20.

Normal-mode output data rate configurations and low-pass cut-off

frequencies

DR1

DR0

Output Data Rate [Hz]

ODR

Low-pass filter cut-off

frequency [Hz]

100

400

292

1000

780

Table 21.

CTRL_REG2 register

BOOT

HPM1

HPM0

FDS

HPen2

HPen1

HPCF1

HPCF0

Table 22.

CTRL_REG2 description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

HPM1, HPM0

High pass filter mode selection. Default value: 00

(00: normal mode; Others: refer to

Table 23)

FDS

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

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