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PRELIMINARY
CY14B101KA/CY14B101MA
Document #: 001-42880 Rev. *C
Page 21 of 29
Software Controlled STORE/RECALL Cycle
Parameters[31, 32]
Description
20 ns
25 ns
45 ns
Unit
Min
Max
Min
Max
Min
Max
tRC
STORE/RECALL Initiation Cycle Time
20
25
45
ns
tSA
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
15
20
30
ns
tHA
Address Hold Time
0
0
0
ns
tRECALL
RECALL Duration
200
200
200
µs
tSS
[33, 34]
Soft Sequence Processing Time
100
100
100
µs
Switching Waveforms
Figure 13. CE & OE Controlled Software STORE/RECALL Cycle [32]
Figure 14. AutoStore Enable/Disable Cycle
t
RC
t
RC
t
SA
t
CW
tCW
tSA
tHA
t
LZCE
t
HZCE
tHA
t
HA
t
HA
t
STORE/tRECALL
t
HHHD
tLZHSB
High Impedance
Address #1
Address #6
Address
CE
OE
HSB(STOREonly)
DQ (DATA)
RWI
tDELAY Note
35
t
RC
t
RC
t
SA
t
CW
t
CW
t
SA
tHA
tLZCE
t
HZCE
t
HA
t
HA
t
HA
t
DELAY
Address #1
Address #6
Address
CE
OE
DQ (DATA)
t
SS
Note
35
Notes
31. The software sequence is clocked with CE controlled or OE controlled reads.
32. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.
33. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
34. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
35. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
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