UCC5630AMWPRSLASH81535 datasheet(4/8 Pages) TI

4 / 8 page

UCC5630A

PIN DESCRIPTIONS

DIFFB:

Input pin for the comparators that select SE,

LVD, or HIPD modes of operation. This pin should be de-

coupled with a 4.7 F capacitor to ground and then cou-

pled to the DIFSENS pin through a 50k

resistor.

DIFSENS: Connects to the Diff Sense line of the SCSI

bus. The bus mode is controlled by the voltage level on

this pin.

DISCNCT: Input pin used to shut down the terminator if

the terminator is not connected at the end of the bus.

Connect this pin to ground to activate the terminator or

open pin to disable the terminator.

HIPD: TTL compatible status bit. This output pin is high

when a high voltage differential device is detected on the

bus.

HS/GND: Heat sink ground pins. These should be con-

nected to large area PC board traces to increase the

power dissipation capability.

GND: Power Supply return.

L1– thru L9–: Termination lines. These are the active

lines in SE mode and are the negative lines for LVD

mode. In HIPD mode, these lines are high impedance.

L1+ thru L9+: Termination lines. These lines switch to

ground in SE mode and are the positive lines for LVD

mode. In HIPD mode, these lines are high impedance.

MSTR/SLV: If the terminator is enabled, this input pin en-

ables / disables the DIFSENS driver, when connected to

TRMPWR or ground respectively. When the terminator is

disabled, the DIFSENS driver is off, independent of this

input.

LVD: TTL compatible status bit. This output pin is high

when the SCSI bus is in LVD mode.

REG:

Regulator output bypass pin. This pin must be

connected to a 4.7 F capacitor to ground.

SE: TTL compatible status bit. This output pin is high

when the SCSI bus is in SE mode.

TRMPWR: 2.7V to 5.25V power input pin, bypass near

the terminators with a 4.7 F capacitor to ground.

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA =TJ = 0°C to 70°C,

TRMPWR = 2.7V to 5.25V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Master/Slave (MSTR/SLV) Input Section

MSTR/SLV Threshold

VTRMPWR = 2.7V

0.8

1.9

VTRMPWR = 3.3V

2.4

VTRMPWR = 5.25V

1.5

3.7

MSTR/SLV Input Current

–1

Status Bits (SE, LVD, HIPD) Output Section

ISOURCE

VLOAD = 2.4V

–8.7

–4

ISINK

VLOAD = 0.5V

VLOAD = 0.4V

Note 1: VCM is applied to all L+ and L– lines simultaneously.

Note 2: VL– is applied to all L– lines simultaneously.

Note 3:

()

() (

)

at V

−

0 5

20 5

;

Note 4: Ensured by design. Not 100% tested in production.

Note 5:

()

−02

; where

VL(X)= Output voltage for each terminator minus output pin (L1– through L9–) with each pin unloaded.

IL(X )= Output current for each terminator minus output pin (L1– through L9–) with the minus output pin forced to 0.2V.

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