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SPT7720 Datasheet(PDF) 8 Page - Cadeka Microcircuits LLC. |
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SPT7720 Datasheet(HTML) 8 Page - Cadeka Microcircuits LLC. |
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8 / 10 page ![]() 8 5/9/01 SPT7720 REFERENCES To save on parts count, design time, and PC board real estate, the SPT7720 utilizes an internal reference. No other external components are required to implement this feature. VOLTAGE REFERENCE CIRCUIT The SPT7720 has an on-board voltage reference circuit (VREF). It is 2.5 volts and is capable of driving 50 µA loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differen- tial converter conversion circuit. ENCODE INPUT The ENCODE input on the SPT7720 can be driven by ei- ther a single-ended or differential clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the duty signal as close to 50% as possible. For TTL/ CMOS single-ended ENCODE inputs, the rise time of the signal also becomes an important consideration. The ENCODE input is 300 Ω into a bipolar differential pair. ENCODE is internally biased to 1.5 V with a Thevenin equivalent of 5.25 k Ω. DIGITAL INPUTS The DS input is 35 Ω into one side of a differential pair. There is a two-diode clamp from DS to DS in both direc- tions. DS is biased to 1.5 V with a Thevenin equivalent of 5.25 k Ω. The DEMUX pin is input to one side of a CMOS differential pair. The other side is internally biased to 1.5 V and does not connect to the outside. DIGITAL OUTPUTS The output circuitry of the SPT7720 has been designed to be able to support two separate output modes. The demuxed (double-wide) mode supports interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 100 MSPS. The output format is straight binary (table I). Table I – Output Data Format Analog Input Output Code D7–D0 +FS 1111 1111 +FS – 1/2 LSB 1111 111Ø +1/2 FS ØØØØ ØØØØ –FS + 1/2 LSB 0000 000Ø –FS 0000 0000 Ø indicates the flickering bit between logic 0 and 1 The data output mode is set using the DEMUX input (pin 42). Table II describes the mode switching options. Table II – Output Data Modes Output Mode DEMUX Interleaved Dual Channel Output 0 Single Channel Data Output (Bank A only 100 MSPS max) 1 EVALUATION BOARD The EB7720 evaluation board is available to aid designers in demonstrating the full performance of the SPT7720. This board includes a clock driver and reset circuit, adjust- able references and common mode, a single-ended to dif- ferential input buffer and a single-ended to differential transformer (1:1). An application note (AN7720) describ- ing the operation of this board, as well as information on the testing of the SPT7720, is also available. Contact the factory for price and availability of the EB7720. |
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