7

12/19/97

SPT7730

Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing

PACKAGE OUTLINE

8-Lead SOIC

A

B

C

D

E

F

G

H

I

J

K

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

A

0.187

0.194

4.80

4.98

B

0.228

0.242

5.84

6.20

C

0.050 typ

1.27 typ

D

0.014

0.019

0.35

0.49

E

0.005

0.010

0.13

0.25

F

0.060

0.067

1.55

1.73

G

0.055

0.060

1.40

1.55

H

0.149

0.156

3.81

3.99

I0

°

8

°

0

°

8

°

J

0.007

0.010

0.19

0.25

K

0.016

0.035

0.41

0.89

Ref Hold

Ref Settling Window

**

Synchronous Mode

*

Single Shot Mode

1

A

2

A

3

A

4

A

11

A

12

A

1

B

2

B

3

B

4

B

Sample

Input

Sample

Input

SC

Clock

rising edge of clock 1A and the falling edge of clock 12A.

The reference settling window can be extended in the

synchronous mode by adding extra clocks between conversion

cycles. The example shown is the minimum number of clocks

required (12) per conversion cycle.

**