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12/14/99

SPT7853

CLOCK INPUT

The SPT7853 is driven from a single-ended input clock. Be-

cause the pipelined architecture operates on the rising edge

of the clock input, the device can operate over a wide range

of input clock duty cycles without degrading the dynamic

performance. The device’s sample rate is 1/2 of the input

clock frequency. (See the timing diagram.)

DIGITAL OUTPUTS

The digital outputs for each channel (D0–D9) are driven by a

feature makes it possible to drive the SPT7853’s CMOS-

compatible outputs with the user’s logic system supply. The

format of the output data (D0–D9) is straight binary. (See

table III.) The outputs are latched on the rising edge of CLK.

These outputs can be switched into a tri-state mode by

bringing OEN high.

Table III – Output Data Information

ANALOG INPUT

OUTPUT CODE

D9-D0

+F.S. + 1/2 LSB

11 1111

1111

+F.S. –1/2 LSB

11 1111

111Ø

+1/2 F.S.

ØØ ØØØØ ØØØØ

+1/2 LSB

00 0000

000Ø

0.0 V

00 0000

0000

(Ø indicates the flickering bit between logic 0 and 1).

DATA AVAILABLE

The Data Available pin goes high when the data output bits

are valid (see figure 1b). Note: Optimal performance of the

data valid pin is achieved when using an input clock with a

minimum span range of

≤1 V (clock low) to ≥4 V (clock high).

EVALUATION BOARD

The EB7853 Evaluation Board is available to aid designers

in demonstrating the full performance of the SPT7853. This

board includes a reference circuit, clock driver circuit, output

data latches and an on-board reconstruction of the digital

data. An application note (AN7853) describing the operation

of this board as well as information on the testing of the

SPT7853 is also available. Contact the factory for price and

availability.

CALIBRATION

The SPT7853 uses an auto-calibration scheme to ensure

10-bit accuracy over time and temperature. Gain and offset

errors are continually adjusted to 10-bit accuracy during

device operation. This process is completely transparent to

the user.

Upon powerup, the SPT7853 begins its calibration algo-

rithm. In order to achieve the calibration accuracy required,

the offset and gain adjustment step size is a fraction of a

10-bit LSB. Since the calibration algorithm is an over-

sampling process, a minimum of 10k clock cycles are re-

quired. This results in a minimum calibration time upon

powerup of 150

µsec. Once calibrated, the SPT7853

remains calibrated over time and temperature.

Since the calibration cycles are initiated on the rising edge

of the clock, the clock must be continuously applied for the

SPT7853 to remain in calibration.

INPUT PROTECTION

All I/O pads are protected with an on-chip protection circuit

shown in figure 6. This circuit provides ESD robustness to

3.5 kV and prevents latch-up under severe discharge condi-

tions without degrading analog transition times.

Figure 6 – On-Chip Protection Circuit

Analog

Pad

120

Ω

120

Ω

POWER SUPPLY SEQUENCING

CONSIDERATIONS

All logic inputs should be held low until power to the device

has settled to the specific tolerances. Avoid power

decoupling networks with large time constants which could