The circuit below is a guideline for interconnecting PCA’s EPF8057S with National DP83840A and DP83223 twister chip set

for 10/100 Mb/s applications.

Further details can be obtained from the chip manufacturer application notes.

Please

consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective

application notes.

Typical insertion loss of the isolation transformer is 0.8dB. This parameter covers the entire spectrum of the encoded

signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust

the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 1-2. Note that insertion loss is only 0.5 dB

max at 100 KHz. This ensures proper operation with transceivers such as ML6673 with any length of cable. Follow the

latest circuit recommendations for ML6673 from Micro Linear Applications group. Circuit designers do not need to use the

pins 4 and 5 for applications with ICS 1890, TSC 78Q2120 or ML6673. These inputs allow more effective connection with

the low impedance drivers of the DP83840A while

providing

balanced drive capability for both

DP83840A and the

DP83223(A). Parts similar to EPF8057S are available from several LAN magnetics vendors.

It is recommended that system designers do not ground the receiver side center tap, via a capacitor. This may worsen

EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.

The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires

pick up from the immediate environment. Their placement and use are to be considered carefully before a design is

finalized.

The “common mode termination” load of 75

Ω shown from the center taps of the secondary may be taken to chassis ground

via a cap of suitable value. This depends upon user’s design, EMI margin etc.

It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit

the plane off at least 0.05 inches away from the chip side pins of EPF8057S. There need not be any ground plane beyond

this point.

For best results, PCB designer should design the outgoing traces preferably to be 50

Ω, balanced and well coupled to

achieve minimum radiation from these traces.

Typical Application Circuit for UTP (only one port shown)

CSF8057Sb

Rev. 2

5/22/97

10/100BX Module for

Multi-port Application

E L E C T R O N I C S I N C .

Other pull down/up resistors not shown, for clarification please refer to National’s application notes.

Notes : 1. See text above for clarification.

2. Hub side connections show only one port.

DP83223

DP83840A

RJ45*

8

7

5

1

4

1

6

3

RXD

TXU

TD

RD

SD

RXI

TXO

PMRD

SD

PMID

Chassis

Ground

2000V

50

Ω

50

Ω

75

Ω

75

Ω

EPF8057S

+

-

+

-

+

-

+

-

+

-

0.10µF {Note 1}

0.1µF

{Note 1}

1000pF

1000pF

Isolation Cap

12.1

Ω

12.1

Ω

34

33

32

40

39

38

7

8

4

5

2

1

+

-

Rcv

Xmit

2

TEL: (818) 892-0761

FAX: (818) 894-5791

http://www.pcainc.com

PCA ELECTRONICS, INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343