1A, 76V, High-Efficiency MAXPower

Step-Down DC-DC Converter

12

______________________________________________________________________________________

Ensure that the ripple specification of the input capaci-

tor exceeds the worst-case capacitor RMS ripple cur-

rent. Use the following equations to calculate the input

capacitor RMS current:

input average current, and

η is the converter efficiency.

The ESR of aluminum electrolytic capacitors increases

significantly at cold temperatures. Use a 1µF or greater

value ceramic capacitor in parallel with the aluminum

electrolytic input capacitor, especially for input voltages

below 8V.

Output Filter Capacitor

The worst-case peak-to-peak and RMS capacitor ripple

current, allowable peak-to-peak output ripple voltage,

and the maximum deviation of the output voltage dur-

ing load steps determine the capacitance and the ESR

requirements for the output capacitors.

The output capacitance and its ESR form a zero, which

improves the closed-loop stability of the buck regulator.

Choose the output capacitor so the ESR zero frequency

to 250mΩ ESR are recommended to ensure the closed-

loop stability, while keeping the output ripple low.

The output ripple is comprised of

capacitor discharge) and

of the capacitor). Use low-ESR tantalum or aluminum

electrolytic capacitors at the output. Assuming that the

contributions from the ESR and capacitor discharge

equal 80% and 20% respectively, calculate the output

capacitance and the ESR required for a specified rip-

ple using the following equations:

400µs. It is important to keep the output rise time at

rise time is directly proportional to the output capacitor.

Use 68µF or lower capacitance at the output to control

the overshoot below 5%.

In a dynamic load application, the allowable deviation

of the output voltage during the fast-transient load dic-

tates the output capacitance value and the ESR. The

output capacitors supply the step load current until the

controller responds with a greater duty cycle. The

loop bandwidth of the converter. The resistive drop

across the capacitor ESR and capacitor discharge

cause a voltage droop during a step load. Use a com-

bination of low-ESR tantalum and ceramic capacitors

for better transient load and ripple/noise performance.

Keep the maximum output-voltage deviation above the

tolerable limits of the electronics being powered.

Assuming a 50% contribution each from the output

capacitance discharge and the ESR drop, use the fol-

lowing equations to calculate the required ESR and

capacitance value:

response time of the controller. Controller response

time is approximately one-third of the reciprocal of the

closed-loop unity-gain bandwidth, 20kHz typically.

PC Board Layout Considerations

Proper PC board layout is essential. Minimize ground

noise by connecting the anode of the Schottky rectifier,

the input bypass capacitor ground lead, and the output

filter capacitor ground lead to a single point (“star”

C

It

V

OUT

STEP

RESPONSE

OQ

=

×

Δ

ESR

V

I

OUT

OESR

STEP

=

Δ

C

I

Vf

OUT

L

OQ

SW

≈

××

Δ

Δ

22

.

ESR

V

I

OUT

OESR

L

= Δ

Δ

f

C

ESR

Z

OUT

OUT

=

××

×

1

2

π

II

I

I

I

D

I

VI

V

II

I

II

I

and D

V

V

PRMS

PK

DC

PK

DC

AVGIN

OUT

OUT

IN

PK

OUT

L

DC

OUT

L

OUT

IN

=+

+

×

()

⎛

⎝

⎞

⎠ ×

=

×

×

=+

=

−

=

22

3

22

,

η

ΔΔ

II

I

where

CRMS

PRMS

AVGIN

=−

22