F25L32PA datasheet(21/36 Pages) ESMT

21 / 36 page

ESMT

F25L32PA

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.0

21/36

Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write-Enable-

Latch bit in the Software Status Register to 1 allowing Write

operations to occur.

The WREN instruction must be executed prior to any Write

(Program/Erase) operation. CE must be driven high before the

WREN instruction is executed.

Figure 21: Write Enable (WREN) Sequence

Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write-Enable-

Latch bit to 0 disabling any new Write operations from occurring.

CE must be driven high before the WRDI instruction is

executed.

Figure 22: Write Disable (WRDI) Sequence

Enable Write Status Register (EWSR)

The Enable Write Status Register (EWSR) instruction arms the

Write Status Register (WRSR) instruction and opens the status

instruction does not have any effect and will be wasted, if it is not

followed immediately by the Write Status Register (WRSR)

instruction. CE must be driven low before the EWSR instruction

is entered and must be driven high before the EWSR instruction

is executed.

SCK

01 2 3 4 5 6 7

MSB

HIGH IMPENANCE

MODE3

MODE0

SCK

01 2 3 4 5 6 7

MSB

HIGH IMPENANCE

MODE3

MODE0

F25L32PA Datasheet(PDF) 21 Page - Elite Semiconductor Memory Technology Inc.