iiiiiPEM

PEM

PEM

PEM

PEM

2.4G

2.4G

2.4G

2.4G

2.4Gb SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

AS4DDR32M72PBG

AS4DDR32M72PBG

Rev. 1.2 06/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

Austin Semiconductor, Inc.

OPERATING MODE

The normal operating mode is selected by issuing a MODE

REGISTER SET command with bits A7-A12 each set to zero,

and bits A0-A6 set to the desired values. A DLL reset is initiated

by issuing a MODE REGISTER SET command with bits A7 and

A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to

the desired values. Although not required, JEDEC specifications

recommend when a LOAD MODE REGISTER command is

issued to reset the DLL, it should always be followed by a

LOAD MODE REGISTER command to select normal operating

mode.

All other combinations of values for A7-A12 are reserved for

future use and/or test modes. Test modes and reserved states

should not be used because unknown operation or

incompatibility with future versions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are

DLL enable/disable, output drive strength, and QFC#. These

functions are controlled via the bits shown in Figure 3. The

extended mode register is programmed via the LOAD MODE

REGISTER command to the mode register (with BA0 = 1 and

BA1 = 0) and will retain the stored information until it is

programmed again or the device loses power. The enabling of

the DLL should always be followed by a LOAD MODE

REGISTER command to the mode register (BA0/BA1 both LOW)

to reset the DLL.

The extended mode register must be loaded when all banks

are idle and no bursts are in progress, and the controller must

wait the specified time before initiating any subsequent

operation. Violating either of these requirements could result

in unspecified operation.

Address Bus

Burst Length

BT

Operating Mode

(BA0 and BA1 must be

"0, 0" to select

the base mode register

(vs. the extended

0*

0*

CAS Latency

* M14 and M13

mode register).

Mode Register (Mx)

M2 M1 M0

M3 = 0

M3 = 1

0

0 0

Reserved

Reserved

0

0 1

2

2

0

1 0

4

4

0

1 1

8

8

1

0 0

Reserved

Reserved

1

0 1

Reserved

Reserved

1

1 0

Reserved

Reserved

1

1 1

Reserved

Reserved

Burst Length

0

1

Sequential

Interleaved

M3

Burst Type

CAS Latency

M6 M5 M4

Reserved

0

00

Reserved

0

0

1

2

0

1

0

Reserved

0

1

1

Reserved

1

0

0

Reserved

1

0

1

2.5

1

1

0

Reserved

1

1

1

M12

M11

M10

M9

M8

M7

M6-M0

Operating Mode

0

0

0

0

0

0

Valid

Normal Operation

0

0

0

0

1

0

id

Val

Normal Operation/Reset DLL

-

-

-

-

--

-

All other states reserved

FIGURE 1 - MODE BURST DEFINITION