iiiiiPEM

PEM

PEM

PEM

PEM

2.4G

2.4G

2.4G

2.4G

2.4Gb SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

AS4DDR32M72PBG

AS4DDR32M72PBG

Rev. 1.2 06/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

13

Austin Semiconductor, Inc.

ELECTRICAL

CHARACTERISTICS

AND

RECOMMENDED

AC

OPERATING

CHARACTERISTICS (NOTES 1-5, 14-17, 33)

Min

Max

Min

Max

-0.70

+0.70

-0.75

+0.75

ns

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CL=2.5 (45, 52)

6

13

7.5

13

ns

CL=2 (45, 52)

7.5

13

8

13

ns

0.45

0.5

ns

0.45

0.5

ns

1.75

1.75

ns

-0.6

+0.6

-0.75

+0.75

ns

tDQSH

0.35

0.35

0.35

0.35

0.45

0.5

ns

0.75

1.25

0.75

1.25

0.2

0.2

0.2

0.2

ns

+0.7

+0.75

ns

-0.7

-0.75

ns

0.75

0.9

ns

0.75

0.9

ns

0.8

1.0

ns

0.8

1.0

ns

12

15

ns

ns

0.55

1

ns

42

70,000

40

120,000

ns

15

15

ns

60

60

ns

72

75

ns

15

15

ns

15

15

ns

0.9

1.1

0.9

1.1

0.4

0.6

0.4

0.6

12

15

ns

0.25

0.25

00

ns

0.4

0.6

0.4

0.6

15

15

ns

11

NA

ns

70.3

70.3

µs

35

35

µs

7.8

7.8

µs

3.9

3.9

µs

00

ns

75

75

ns

200

200

Symbol

@CL=2.5 [CL=2]

-6, 333 [266] Mbps

Units

-75, 266 [250] Mbps

@CL=2.5 [CL=2]

Exit SELF REFRESH to non-READ command

Exit SELF REFRESH to READ command

Clock cycle time

Parameter

REFRESH to REFRESH command interval (Military temp only) (23)

Average periodic refresh interval (Commercial & Industrial temp only) (23)

Average periodic refresh interval (Military temp only) (23)

Terminating voltage delay to Vcc (53)

Write recovery time

Internal WRITE to READ command delay

REFRESH to REFRESH command interval (Commercial & Industrial temp

Active bank a to ACTIVE bank b command

DQS write preamble

DQS write preamble setup time (20,21)

DQS write postamble (19)

PRECHARGE command period

DQS read preamble (42)

DQS read postamble

Data valid output window (25)

ACTIVE to READ with Auto precharge command

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period (50)

ACTIVE to READ or WRITE delay

LOAD MODE REGISTER command cycle time

DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)

Data hold skew factor

ACTIVE to PRECHARGE command (35)

Address and control input hold time (fast slew rate) (14)

Address and control input setup time (fast slew rate) (14)

Address and control input hold time (slow slew rate) (14)

Address and control input setup time (slow slew rate) (14)

DQS falling edge to CLK rising - hold time

Half clock period (34)

Data-out high-impedance window from CLK/CLK# (18, 42)

Data-out low-impedance window from CLK/CLK# (18, 43)

DQS input high pulse width

DQS-DQ skew, DQS to last valid, per group, per access (25,26)

Write command to first DQS latching transition

DQS falling edge to CLK rising - setup time

DQ and DM input setup time relative to DQS (26,31)

DQ and DM input pulse with (for each input) (31)

Access window of DQS from CLK/CLK#

DQS input high pulse width

Access window of DQs from CLK/CLK#

CLK high-level width (30)

CLK low-level width (30)

DQ and DM input hold time relative to DQS (26, 31)