AD9267

Rev. 0 | Page 5 of 24

DIGITAL SPECIFICATIONS

All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,

unless otherwise noted.

Table 3.

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS1/LVDS/LVPECL

Differential Input Voltage

Full

0.4

0.8

2

V p-p

Input Common-Mode Range

Full

450

mV

High Level Input Current

Full

−60

+60

μA

Low Level Input Current

Full

−60

+60

μA

Input Resistance

Full

20

kΩ diff

Input Capacitance

Full

1

pF

LOGIC INPUTS (SCLK)

High Level Input Voltage

Full

1.2

DRVDD + 0.3

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−50

−75

μA

Low Level Input Current

Full

−10

+10

μA

Input Resistance

Full

30

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUTS (SDIO, CSB, RESET)

High Level Input Voltage

Full

1.2

DRVDD + 0.3

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−10

+10

μA

Low Level Input Current

Full

+40

+135

μA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

DIGITAL OUTPUTS (D0±x to D3±x)

ANSI-644

Logic Compliance

LVDS

Full

247

454

mV

Full

1.125

1.375

V

Output Coding (Default)

Twos complement

Low Power, Reduced Signal Option

Logic Compliance

LVDS

Full

150

250

mV

Full

1.10

1.30

V

Output Coding (Default)

Twos complement