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AD9572ACPZLVD-R7 Datasheet(PDF) 8 Page - Analog Devices |
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AD9572ACPZLVD-R7 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page ![]() AD9572 Rev. 0 | Page 8 of 20 TIMING DIAGRAMS DIFFERENTIAL LVPECL 80% 20% tRP tFP SINGLE-ENDED CMOS 5pF LOAD 80% 20% tRC Figure 3. LVPECL Timing, Differential DIFFERENTIAL LVDS 80% 20% tRL tFL Figure 4. LVDS Timing, Differential tFC Figure 5. CMOS Timing, Single-Ended, 5 pF Load |
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