XRT86VL3X datasheet(9/154 Pages) EXAR

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XRT86VL3X

REV. 1.2.3

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

Figure 104.: Frame/Byte Format of the CAS Multi-Frame Structure ............................................................................. 115

Figure 105.: E1 Frame Format ...................................................................................................................................... 116

Figure 106.: T1 Frame Format ....................................................................................................................................... 117

Figure 107.: T1 Superframe PCM Format ..................................................................................................................... 118

Figure 108.: T1 Extended Superframe Format .............................................................................................................. 119

Figure 109.: T1DM Frame Format ................................................................................................................................. 121

Figure 110.: Framer System Transmit Timing Diagram (Base Rate/Non-Mux) ............................................................. 125

Figure 111.: Framer System Receive Timing Diagram (RxSERCLK as an Output) ...................................................... 126

Figure 112.: Framer System Receive Timing Diagram (RxSERCLK as an Input) ......................................................... 127

Figure 113.: Framer System Transmit Timing Diagram (HMVIP and H100 Mode) ....................................................... 128

Figure 114.: Framer System Receive Timing Diagram (HMVIP/H100 Mode) ............................................................... 129

Figure 115.: Framer System Transmit Overhead Timing Diagram ................................................................................ 130

Figure 116.: Framer System Receive Overhead Timing Diagram (RxSERCLK as an Output) ..................................... 131

Figure 117.: Framer System Receive Overhead Timing Diagram (RxSERCLK as an Input) ........................................ 131

Figure 118.: ITU G.703 Pulse Template ........................................................................................................................ 135

Figure 119.: DSX-1 Pulse Template (normalized amplitude) ........................................................................................ 136

Figure 120.: Intel µP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Not Tied ’HIGH’

137

Figure 121.: Intel µP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Tied ’HIGH’ 139

Figure 122.: Motorola Asychronous Mode Interface Signals During Programmed I/O Read and Write Operations ..... 140

Figure 123.: Power PC 403 Interface Signals During Programmed I/O Read and Write Operations ........................... 141

Figure 124.: DMA Write Cycle Timing Waveform .......................................................................................................... 142

Figure 125.: DMA Read Cycle Timing Waveform .......................................................................................................... 142

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