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MPC2F35L Datasheet(PDF) 12 Page - Megawin Technology Co., Ltd

Part # MPC2F35L
Description  Low-speed USB micro-controller
PDF  46 Pages
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Manufacturer  MEGAWIN [Megawin Technology Co., Ltd]
Direct Link  http://www.megawin.com.tw/megawin_EN/Index.asp
Logo MEGAWIN - Megawin Technology Co., Ltd

MPC2F35L Datasheet(HTML) 12 Page - Megawin Technology Co., Ltd

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MPC2F35_USB Data Sheet
MEGAWIN
TM0
FTM0_UV Frequency
00H
Invalid
01H
93.75 KHz
02H
62.5 KHz
…
…
FFH
732.42 Hz
General Purpose I/O Ports
Port 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
00D0H
P0_BUF
BP07
BP06
BP05
BP04
BP03
BP02
BP01
BP00
√
√
00D8H
P0
P07
P06
P05
P04
P03
P02
P01
P00
√
-
0240H
P0_CR
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
√
√
0241H
P0_MR
-
-
MP05
MP04
-
-
MP01
MP00
√
√
Port 0 is an 8-bit I/O port; each pin can be programmed as input or output individually.
P0_BUF: Port 0 output buffer. When P0.n is configured as an output pin, it outputs the content
of P0_BUF.n.
P0: Values on the pin of Port 0 while reading from Port 0.
P0_CR: Configure P0.0 ~ P0.7 to be input or output individually. 0: Input (default), 1: Output
P0_MR: Configure the output mode of P0.0 ~ P0.7 with a 17k ohm pull-high resistor, CMOS or
NMOS open drain
−
MP00 (P0_MR.0): P0.0 ~ P0.3 with the pull-high control bit, 0: Disable (default), 1:Enable
−
MP01 (P0_MR.1): P0.0 ~ P0.3 with the CMOS or NMOS selector, 0: CMOS (default), 1: NMOS
−
MP04 (P0_MR.4): P0.4 ~ P0.7 with the pull-high control bit, 0: Disable (default), 1: Enable
−
MP05 (P0_MR.5): P0.4 ~ P0.7 with the CMOS or NMOS selector, 0: CMOS (default), 1: NMOS
At initial reset, Port 0 is all in the input mode. Each pin of Port 0 can be specified as the input or output
mode independently by the P0_CR SFR. When Port 0 is used as the output port, CMOS or NMOS
open drain output type can be selected by the P0_MR register. Port 0 has 17k ohm internal pull-high
resistors that can be enabled/disabled by specifying the MP00 and MP04 in the P0_MR register
respectively. The pull-high resistor is automatically disabled only when the port is configured as CMOS
output. Schmitt trigger circuit is added in the input path of P0.0~P0.3. User should be carefully on
setting pin as input with no pull high resistor since this setting has potential to cause leakage.
When P0.4 and P0.5 are set as input pins, they are INT0 and INT1 interrupt sources. A falling edge at
the two pins will set the corresponding bits in the IRQ_ST register to 1, and the external interrupt
subroutines will be executed if the corresponding bits in the IRQ_EN register are also set.
Port 1



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