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STM32F101XC Datasheet(PDF) 58 Page - STMicroelectronics

Part # STM32F101XC
Description  High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces
PDF  106 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101XC Datasheet(HTML) 58 Page - STMicroelectronics

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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
58/106
Doc ID 14610 Rev 7
Figure 23.
Asynchronous multiplexed NOR/PSRAM read waveforms
Table 32.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
1.
CL = 15 pF.
2.
Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3THCLK – 1
3THCLK + 2
ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
THCLK – 0.5
THCLK + 1.5
ns
tw(NWE)
FSMC_NWE low time
THCLK – 0.5
THCLK + 1.5
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
7.5
ns
th(A_NWE)
Address hold time after FSMC_NWE high
THCLK
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
1.5
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
THCLK – 0.5
ns
tv(Data_NE)
FSMC_NEx low to Data valid
THCLK + 7
ns
th(Data_NWE) Data hold time after FSMC_NWE high
THCLK
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
5.5
ns
tw(NADV)
FSMC_NADV low time
THCLK + 1.5
ns
NBL
Data
FSMC_NBL[1:0]
FSMC_AD[15:0]
tv(BL_NE)
th(Data_NE)
Address
FSMC_A[25:16]
tv(A_NE)
FSMC_NWE
t v(A_NE)
ai14892b
Address
FSMC_NADV
t v(NADV_NE)
tw(NADV)
tsu(Data_NE)
th(AD_NADV)
FSMC_NE
FSMC_NOE
tw(NE)
t w(NOE)
tv(NOE_NE)
t h(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
th(Data_NOE)



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