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24LCS22A Datasheet(PDF) 3 Page - Microchip Technology |
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24LCS22A Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 26 page  © 2009 Microchip Technology Inc. DS21682E-page 3 24LCS22A TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Vcc = +2.5V to 5.5V Industrial (I): TA = -40°C to +85°C Param. No. Sym Parameter Min Max Units Conditions 1FCLK Clock frequency — — 100 400 kHz 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 2THIGH Clock high time 4000 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 3TLOW Clock low time 4700 1300 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 4TR SDA and SCL rise time — — 1000 300 ns 2.5V ≤ VCC ≤ 5.5V (Note 1) 4.5V ≤ VCC ≤ 5.5V (Note 1) 5TF SDA and SCL fall time — — 300 300 ns (Note 1) 6THD:STA Start condition hold time 4000 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 7TSU:STA Start condition setup time 4700 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 8THD:DAT Data input hold time 0 0 — — ns (Note 2) 9TSU:DAT Data input setup time 250 100 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 10 TSU:STO Stop condition setup time 4000 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 11 TAA Output valid from clock (Note 2) — — 3500 900 ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 12 TBUF Bus free time: Time the bus must be free before a new transmission can start 4700 1300 — — ns 2.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 13 TOF Output fall time from VIH minimum to VIL maximum — 20+0.1CB 250 250 ns 2.5V ≤ VCC ≤ 5.5V (Note 1) 4.5V ≤ VCC ≤ 5.5V (Note 1) 14 TSP Input filter spike suppression (SDA and SCL pins) — — 50 50 ns (Notes 1 and 3) 15 TWR Write cycle time (byte or page) — — 10 10 ms 16 TVAA Output valid from VCLK — — 2000 1000 ns 17 TVHIGH VCLK high time 4000 600 — — ns 18 TVLOW VCLK low time 4700 1300 — — ns 19 TVHST VCLK setup time 0 0 — — ns 20 TSPVL VCLK hold time 4000 600 — — ns 21 TVHZ Mode transition time — — 1000 500 ns 22 TVPU Transmit-only power-up time 0 0 — — ns 23 TSPV Input filter spike suppression (VCLK pin) — — 100 100 ns 24 — Endurance 1M — cycles 25°C, VCC = 5.0V, Block mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. |
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