MPL115A1 datasheet(4/8 Pages) FREESCALE

4 / 8 page

MPL115A1

Sensors

Freescale Semiconductor

Pressure

Coefficient Bit-Width Specs

The table below specifies the initial coefficient bit-width specs for the compensation algorithm.

Example Binary Format Definitions:

Sign = 0, Integer Bits = 8, Fractional Bits = 4 :

Coeff = S I7 I6 I5 I4 I3 I2 I1 I0 . F3 F2 F1 F0

Sign = 1, Integer Bits = 4, Fractional Bits = 7 :

Coeff = S I3 I2 I1 I0 . F6 F5 F4 F3 F2 F1 F0

Sign = 0, Integer Bits = 0, Fractional Bits = 6, dec pt zero pad = 2 : Coeff = S 0 . 0 0 F5 F4 F3 F2 F1 F0

Sign = 0, Integer Bits = 0, Fractional Bits = 5, dec pt zero pad = 3 : Coeff = S 0 . 0 0 0 F4 F3 F2 F1 F0

NOTE: Negative coefficients (Sign = 1) are coded in 2’s complement notation.

Coefficient Address Map

For coefficients with less than 16 bits, the lower lsbs are zero. For example, c11 is 11 bits and is stored into 2 bytes as follows:

c11 MS byte = c11[10:3] = [c11b10 , c11b9 , c11b8 , c11b7 , c11b6 , c11b5 , c11b4 , c11b3]

NOTE: c11 LS byte = c11[2:0] & “00000” = [c11b2 , c11b1 , c11b0 , 0 , 0 , 0 , 0 , 0]

10-bit Output: Compensation Coefficient Specs

Total

Coeff.

Bits

c12

c11

c22

Total Bits

Sign Bits

Integer Bits

Fractional Bits

dec pt zero pad

—

Address

Coefficient

$04

a0 MS Byte

$05

a0 LS Byte

$06

b1 MS Byte

$07

b1 LS Byte

$08

b2 MS Byte

$09

b2 LS Byte

$0A

c12 MS Byte

$0B

c12 LS Byte

$0C

c11 MS Byte

$0D

c11 LS Byte

$0E

c22 MS Byte

$0F

c22 LS Byte

MPL115A1 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

MPL115A1 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8

Datasheet Download

Link URL