PCIMX511AJM6C datasheet(13/160 Pages) FREESCALE

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Electrical Characteristics

i.MX51A Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX51Aprocessor.

3.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 5 for a quick reference

to the individual tables and sections.

VREF

When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the

NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a

1 k

Ω 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor

with a closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 k

Ω 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the ± 2% VREF tolerance (per the DDR-2 specification) is

maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider.

Note: When VREF is used with mDDR this signal must be tied to GND.

VREFOUT

This signal determines the Triple Video DAC (TVDAC) reference voltage. The user must tie

VREFOUT to an external 1.18 k

Ω 1% resistor to GND.

VREG

This regulator is no longer used and should be floated by the user.

XTAL/EXTAL

The user should tie a fundamental-mode crystal across XTAL and EXTAL. The crystal must be

rated for a maximum drive level of 100

μW or higher. An ESR (equivalent series resistance) of

Ω or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz

on EXTAL.

The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must

be directly driven by the external oscillator and XTAL is floated. The EXTAL signal level must swing

from NVCC_OSC to GND. If the clock is used for USB, then there are strict jitter requirements: <

50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY.

The COSC_EN bit in the CCM (Clock Control Module) must be cleared to put the on-chip oscillator

circuit in bypass mode which allows EXTAL to be externally driven. COSC_EN is bit 12 in the CCR

Table 4. JTAG Controller Interface Summary

JTAG

I/O Type

On-chip Termination

JTAG_TCK

Input

100 k

Ω pull-down

JTAG_TMS

Input

47 k

Ω pull-up

JTAG_TDI

Input

47 k

Ω pull-up

JTAG_TDO

3-state output

Keeper

JTAG_TRSTB

Input

47 k

Ω pull-up

JTAG_DE_B

Input/open-drain output

47 k

Ω pull-up

JTAG_MOD

Input

100 k

Ω pull-down

Table 3. Special Signal Considerations (continued)

Signal Name

Remarks

PCIMX511AJM6C Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

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