ADN4604ASVZ datasheet(19/40 Pages) AD

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ADN4604

Rev. 0 | Page 19 of 40

TRANSMITTERS

Output Structure and Output Levels

The ADN4604 transmitter outputs incorporate 50 Ω termin-

ation resistors, ESD protection, and output current switches.

Each channel provides independent control of both the absolute

output level and the preemphasis output level. Note that the

choice of output level affects the output common-mode level.

ON-CHIP TERMINATION

ESD

VCC

VTTOx

OPx

ONx

Ω

VEE

IDC + IPE

Figure 42. Simplified TX Output Circuit

Preemphasis

Transmission line attenuation can be equalized at the trans-

mitter using preemphasis. The transmit equalizer setting can

be chosen by matching the channel loss to the amount of boost

provided by the preemphasis.

Basic Settings

In the basic mode of operation, predefined preemphasis settings

are available through a lookup table. Each table entry requires

two bytes of memory. The amount of preemphasis provided

is independent of the full-scale current output. Transmitter

preemphasis levels, as well as dc output levels, can be set

through the serial control interface. The output level and

amount of preemphasis can be independently programmed

through advanced registers. By default, however, the total

output amplitude and preemphasis setting space is reduced

to a single table of basic settings that provides eight levels of

output equalization to ease programming for typical FR4

channels.

Table 10 summarizes the absolute output level, preemphasis

level, and high frequency boost for control setting. The full

resolution of eight settings is available through the serial

interface by writing to Bits[2:0] (the TX PE[2:0] bits) of the

Basic TX Control registers shown in Table 11. A single setting

is programmed to all outputs simultaneously by writing to the

0x18 broadcast address.

The TX has four possible output enable states (disabled,

standby, squelched, and enabled) controlled by the TX EN[1:0]

bits as shown in Table 11. Disabled is the lowest power-down

state. When squelched, the output voltage at both P and N

outputs will be the common-mode voltage as defined by the

output current settings. In standby, the output level of both P

and N outputs will be pulled up to the termination supply

(VTTON or VTTOS).

The TX CTL SELECT bit (Bit 6) in the TX[15:0] basic control

current controls for the channel of interest are selected from

the predefined lookup table or directly from the TX[15:0]

Drive Control[1:0] registers (per channel). Figure 43 is an

illustration of the TX control circuit. Setting the TX CTL

SELECT bit low (default setting) selects preemphasis control

from the predefined, optimized lookup table (Address 0x60

to Address 0x6F).

TABLE

ENTRY 0

TABLE

ENTRY 1

TABLE

ENTRY 2

TABLE

ENTRY 3

TABLE

ENTRY 4

TABLE

ENTRY 5

TABLE

ENTRY 6

TABLE

ENTRY 7

PE[2:0]

TX CTL

SELECT

IPx

OPx

INx

ONx

PER OUTPUT PORT

LOOKUP TABLE

BASIC SETTINGS

PER PORT

OUTPUT LEVEL

ADVANCED SETTINGS

TX EN[1:0]

Figure 43. Transmitter Control Block Diagram

In applications where the default preemphasis settings in the

lookup table are not sufficient, the lookup table entries can be

modified by programming the TX lookup table registers (0x60

to 0x6F) shown in Table 12. In applications where the eight

table entries are insufficient, each output can be programmed

individually.

Table 10. Preemphasis Boost and Overshoot vs. Setting

Setting

Main Tap

Current

(mA)

Delayed Tap

Current (mA)

Boost

(dB)

Overshoot

(%)

DC Swing

(mV p-p)

0.0

800

2.0

800

4.2

62.5

800

6.0

100

800

7.8

145

550

9.5

200

400

12.0

300

12.0

300

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