ICS8430002AY REVISION C NOVEMBER 12, 2009

7

©2009 Integrated Device Technology, Inc.

ICS8430002 Data Sheet

HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

↑ = Rising edge transition

↓ = Falling edge transition

Table 3B. Programmable VCO Frequency Function Table, P = ÷1

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 25MHz.

Inputs

Conditions

MR

nP_LOAD

M

N

S_LOAD

S_CLOCK

S_DATA

H

X

X

X

X

X

X

Reset. Forces outputs LOW.

L

L

Data

Data

X

X

X

Data on M and N inputs passed directly to the M divider

and N output divider. TEST output forced LOW.

L

↑

Data

Data

L

X

X

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

LH

X

X

L

↑

Data

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

LH

X

X

↑

LData

Contents of the shift register are passed to the

M divider and N output divider.

LH

X

X

↓

L

Data

M divider and N output divider values are latched.

L

H

X

X

L

X

X

Parallel or serial input does not affect shift registers.

LH

X

X

H

↑

Data

S_DATA passed directly to M divider as it is clocked.

VCO Frequency

(MHz)

M Divide

32

16

8

4

2

1

M5

M4

M3

M2

M1

M0

500

20

0

10

10

0

•

•

••

••

••

550

22

0

10

11

0

•

•

••

••

••

625

25

0

11

00

1