AT91SAM9G45 datasheet(49/54 Pages) ATMEL

49 / 54 page

6438CS–ATARM–13-Oct-09

AT91SAM9G45

• MII or RMII interface to the physical layer

• Register Interface to address, data, status and control registers

• DMA Interface, operating as a master on the Memory Controller

• Interrupt generation to signal receive and transmit completion

• 128-byte transmit and 128-byte receive FIFOs

• Automatic pad and CRC generation on transmitted frames

• Address checking logic to recognize four 48-bit addresses

• Supports promiscuous mode where all valid frames are copied to memory

• Supports physical layer management through MDIO interface

• Supports Wake On Lan. The receiver supports Wake on LAN by detecting the following

events on incoming receive frames:

– Magic packet

– ARP request to the device IP address

– Specific address 1 filter match

– Multicast hash filter match

10.14 Image Sensor Interface (ISI)

• ITU-R BT. 601/656 8-bit mode external interface support

• Support for ITU-R BT.656-4 SAV and EAV synchronization

• Vertical and horizontal resolutions up to 2048 x 2048

• Preview Path up to 640*480

• Support for packed data formatting for YCbCr 4:2:2 formats

• Preview scaler to generate smaller size image

10.15 8-channel DMA (DMA)

• Acting as two Matrix Masters

• Embeds 8 unidirectional channels with programmable priority

• Address Generation

– Source/Destination address programming

– Address increment, decrement or no change

– DMA chaining support for multiple non-contiguous data blocks through use of linked

lists

– Scatter support for placing fields into a system memory area from a contiguous

transfer. Writing a stream of data into non-contiguous fields in system memory

– Gather support for extracting fields from a system memory area into a contiguous

transfer

– User enabled auto-reloading of source, destination and control registers from initially

programmed values at the end of a block transfer

– Auto-loading of source, destination and control registers from system memory at end

of block transfer in block chaining mode

– Unaligned system address to data transfer width supported in hardware

• Channel Buffering

AT91SAM9G45 Datasheet(PDF) 49 Page - ATMEL Corporation

AT91SAM9G45 Datasheet(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL