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AT32AP7002-CTUT Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT32AP7002-CTUT Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 52 page  4 32054FS–AVR32–09/09 AT32AP7002 2. Blockdiagram Figure 2-1. Blockdiagram DATA[11..0] HSYNC VSYNC PCLK AP CPU NEXUS CLASS 3 OCD INSTR CACHE DATA CACHE TIMER/COUNTER 0/1 INTERRUPT CONTROLLER REAL TIME COUNTER PERIPHERAL DMA CONTROLLER INTRAM0 INTRAM1 HSB-PB BRIDGE B HSB-PB BRIDGE A S M M M S S S M EXTERNAL INTERRUPT CONTROLLER HIGH SPEED BUS MATRIX PIXEL COPROCESSOR RESET_N PA PB PC PD PE A[2..0] B[2..0] CLK[2..0] EXTINT[7..0] KPS[7..0] NMI_N GCLK[3..0] XIN32 XOUT32 XIN0 XOUT0 PA PB PC PD PE NCS[5,4,2] CFRNW, CFCE1, CFCE2, ADDR[23..25] NWAIT DATA[15..0] USB INTERFACE DMA D- D+ 32 KHz OSC OSC0 PLL0 PS2 INTERFACE SERIAL PERIPHERAL INTERFACE 0/1 TWO-WIRE INTERFACE MISO, MOSI NPCS[3..1] SCL SDA USART0 USART1 USART2 USART3 RXD TXD CLK RTS, CTS SYNCHRONOUS SERIAL CONTROLLER 0/1/2 TX_CLOCK, TX_FRAME_SYNC RX_DATA TX_DATA RX_CLOCK, RX_FRAME_SYNC WATCHDOG TIMER XIN1 XOUT1 OSC1 PLL1 SCK JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N TCK TDO TDI TMS POWER MANAGER RESET CONTROLLER SLEEP CONTROLLER CLOCK CONTROLLER CLOCK GENERATOR CONFIGURATION REGISTERS BUS MEMORY MANAGEMENT UNIT PB PB HSB HS B NPCS0 M S CLOCK[1..0] DATA[1..0] HSB-HSB BRIDGE TRST_N DATA[31..16] OSCEN_N PLL0 PLL1 DMA CONTROLLER S M M AUDIO BITSTREAM DAC MULTIMEDIA CARD INTERFACE AC97 CONTROLLER SCLK SDI SSYNC SDO CLK CMD DATA[7..0] DATA0 DATA1 DATA0N DATA1N PULSE WIDTH MODULATION CONTROLLER PWM0 PWM1 PWM2 PWM3 IMAGE SENSOR INTERFACE M LCD CONTRO LLER DMA M S VSYNC, HSYNC, PWR, PCLK, MODE, DVAL, CC, DATA[22..0], GPL[7..0] RAS, CAS, SDWE, NANDOE, NANDWE, SDCK, SDCKE, NWE3, NWE1, NWE0, NRD, NCS[3,1,0], ADDR[22..0] |
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