ATmega162 datasheet(189/324 Pages) ATMEL

189 / 324 page

189

2513K–AVR–07/09

ATmega162/V

USART Control and

Status Register C –

UCSRC

(1)

Note:

1. The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Access-

ing UBRRH/ UCSRC Registers” on page 184 section which describes how to access this

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when

reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If

a mismatch is detected, the UPE Flag in UCSRA will be set.

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the transmitter. The receiver ignores

this setting.

Bit

765

4321

URSEL

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

UCSRC

Read/Write

R/W

Initial Value

100

0011

Table 73. UMSEL Bit Settings

UMSEL

Mode

Asynchronous Operation

Synchronous Operation

Table 74. UPM Bits Settings

UPM1

UPM0

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

Table 75. USBS Bit Settings

USBS

Stop Bit(s)

01-bit

12-bit

ATmega162 Datasheet(PDF) 189 Page - ATMEL Corporation

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