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AT89LP213 Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT89LP213 Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 98 page  6 3538D–MICRO–10/09 AT89LP213/214 5. Comparison to Standard 8051 The AT89LP213/214 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the standard 8051 are outlined in the following paragraphs. 5.1 System Clock The CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer divided by 2 to provide the internal clock and x2 mode is not supported. 5.2 Instruction Execution with Single-cycle Fetch The CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock cycles. See “Instruction Set Summary” on page 60 for more details. 5.3 Interrupt Handling The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle. The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response, this leads to a higher maximum rate of incidence for the external interrupts. 5.4 Timer/Counters By default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the prescaler (Table 9-2 on page 14). Setting TPS = 1011B will cause the timers to count once every 12 clocks. The external Timer/Counter pins, T0 and T1, are sampled at every clock cycle instead of once every 12 clock cycles. This increases the maximum rate at which the Counter modules may function. 5.5 Serial Port The baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock fre- quency in the standard 8051; and output data is only stable around the rising edge of the serial clock. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP214 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates. |
Similar Part No. - AT89LP213_09 |
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Similar Description - AT89LP213_09 |
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