ATmega165 datasheet(170/336 Pages) ATMEL

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ATmega165/V

2573G–AVR–07/09

•Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

USART Baud Rate Registers –

UBRRL and UBRRH

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit

must be written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the

four most significant bits, and the UBRRL contains the eight least significant bits of the

USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-

rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of

the baud rate prescaler.

Table 70. UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

000

5-bit

001

6-bit

010

7-bit

011

8-bit

100

Reserved

101

Reserved

110

Reserved

111

9-bit

Table 71. UCPOL Bit Settings

UCPOL

Transmitted Data Changed (Output of

TxD Pin)

Received Data Sampled (Input on

RxD Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

Bit

151413121110

––––

UBRR[11:8]

UBRRH

UBRR[7:0]

UBRRL

7654

321

Read/Write

R/W

Initial Value

0000

000

0000

000

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