ATmega165 datasheet(215/336 Pages) ATMEL

215 / 336 page

215

ATmega165/V

2573G–AVR–07/09

The active states are:

•

Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; 0xF

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

•

Capture-DR: Loads a logic “0” into the Bypass Register.

•

Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Related

MCU Control Register –

MCUCR

The MCU Control Register contains control bits for general MCU functions.

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.

If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling

or enabling of the JTAG interface, a timed sequence must be followed when changing

this bit: The application software must write this bit to the desired value twice within four

cycles to change its value. Note that this bit must not be altered when using the On-chip

Debug system.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be

set to one. The reason for this is to avoid static current at the TDO pin in the JTAG

interface.

Bit

765

432

JTD

–

PUD

–

IVSEL

IVCE

MCUCR

Read/Write

R/W

Initial Value

ATmega165 Datasheet(PDF) 215 Page - ATMEL Corporation