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AT25DF161 Datasheet(PDF) 50 Page - ATMEL Corporation |
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AT25DF161 Datasheet(HTML) 50 Page - ATMEL Corporation |
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50 / 60 page ![]() 50 3687C–DFLASH–7/09 AT25DF161 [Preliminary] VIH Input High Voltage 0.7 x VCC V VOL Output Low Voltage IOL = 1.6 mA; VCC = Min 0.4 V VOH Output High Voltage IOH = -100 µA; VCC = Min VCC - 0.2V V 15.4 AC Characteristics – Maximum Clock Frequencies Symbol Parameter Min Max Units RapidS and SPI Operation fMAX Maximum Clock Frequency for All Operations – RapidS Operation Only (excluding 0Bh, 03h, 3Bh, and 9F opcodes) 100 MHz fCLK Maximum Clock Frequency for All Operations (excluding 03h and 3Bh opcodes) 85 MHz fRDLF Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency) 50 MHz fRDDO Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read) 85 MHz 15.5 AC Characteristics – All Other Parameters Symbol Parameter Min Max Units tCLKH Clock High Time 4.3 ns tCLKL Clock Low Time 4.3 ns tCLKR (1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCLKF (1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCSH Chip Select High Time 50 ns tCSLS Chip Select Low Setup Time (relative to Clock) 5 ns tCSLH Chip Select Low Hold Time (relative to Clock) 5 ns tCSHS Chip Select High Setup Time (relative to Clock) 5 ns tCSHH Chip Select High Hold Time (relative to Clock) 5 ns tDS Data In Setup Time 2ns tDH Data In Hold Time 1ns tDIS (1) Output Disable Time 5ns tV (2) Output Valid Time 5ns tOH Output Hold Time 2ns tHLS HOLD Low Setup Time (relative to Clock) 5 ns tHLH HOLD Low Hold Time (relative to Clock) 5 ns tHHS HOLD High Setup Time (relative to Clock) 5 ns tHHH HOLD High Hold Time (relative to Clock) 5 ns tHLQZ(1) HOLD Low to Output High-Z 5ns tHHQX(1) HOLD High to Output Low-Z 5ns tWPS (1)(3) Write Protect Setup Time 20 ns 15.3 DC Characteristics Symbol Parameter Condition Min Typ Max Units |
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