AT91SAM9263-CU datasheet(29/1110 Pages) ATMEL

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6249H–ATARM–27-Jul-09

AT91SAM9263 Preliminary

9.2

Reset Controller

• Based on two Power-on-Reset cells

– One on VDDBU and one on VDDCORE

• Status of the last reset

– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software

reset, user reset or watchdog reset

• Controls the internal resets and the NRST pin output

– Allows shaping a reset signal for the external devices

9.3

Shutdown Controller

• Shutdown and Wake-up logic

– Software programmable assertion of the SHDN pin (SHDN is push-pull)

– Deassertion programmable on a WKUP pin level change or on alarm

9.4

Clock Generator

• Embeds the low-power 32768 Hz Slow Clock Oscillator

– Provides the permanent Slow Clock SLCK to the system

• Embeds the Main Oscillator

– Oscillator bypass feature

– Supports 3 to 20 MHz crystals

• Embeds 2 PLLs

– Output 80 to 240 MHz clocks

– Integrates an input divider to increase output accuracy

– 1 MHz Minimum input frequency

Figure 9-2.

Clock Generator Block Diagram

Power

Management

Controller

XIN

XOUT

PLLRCA

Slow Clock

SLCK

Main Clock

MAINCK

PLLA Clock

PLLACK

Control

Status

PLL and

Divider B

PLLRCB

PLLB Clock

PLLBCK

XIN32

XOUT32

Slow Clock

Oscillator

Main

Oscillator

PLL and

Divider A

Clock Generator

AT91SAM9263-CU Datasheet(PDF) 29 Page - ATMEL Corporation

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