AT91SAM9G45-CU datasheet(44/1159 Pages) ATMEL

44 / 1159 page

6438D–ATARM–13-Oct-09

AT91SAM9G45

9.6

Memory Management Unit (MMU)

The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir-

tual memory features required by operating systems like Symbian OS®, Windows CE®, and

Linux

®. These virtual memory features are memory access permission controls and virtual to

physical address translations.

The Virtual Address generated by the CPU core is converted to a Modified Virtual Address

(MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The

MMU translates modified virtual addresses to physical addresses by using a single, two-level

page table set stored in physical memory. Each entry in the set contains the access permissions

and the physical address that correspond to the virtual address.

The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These

entries contain a pointer to either a 1 MB section of physical memory along with attribute infor-

mation (access permissions, domain, etc.) or an entry in the second level translation tables;

coarse table and fine table.

The second level translation tables contain two subtables, coarse table and fine table. An entry

in the coarse table contains a pointer to both large pages and small pages along with access

permissions. An entry in the fine table contains a pointer to large, small and tiny pages.

Table 7 shows the different attributes of each page in the physical memory.

The MMU consists of:

• Access control logic

• Translation Look-aside Buffer (TLB)

• Translation table walk hardware

9.6.1

Access Control Logic

The access control logic controls access information for every entry in the translation table. The

access control logic checks two pieces of access information: domain and access permissions.

The domain is the primary access control mechanism for a memory region; there are 16 of them.

It defines the conditions necessary for an access to proceed. The domain determines whether

the access permissions are used to qualify the access or whether they should be ignored.

The second access control mechanism is access permissions that are defined for sections and

for large, small and tiny pages. Sections and tiny pages have a single set of access permissions

whereas large and small pages can be associated with 4 sets of access permissions, one for

each subpage (quarter of a page).

9.6.2

Translation Look-aside Buffer (TLB)

The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going

through the translation process every time. When the TLB contains an entry for the MVA (Modi-

Table 9-6.

Mapping Details

Mapping Name

Mapping Size

Access Permission By

Subpage Size

Section

1M byte

Section

Large Page

64K bytes

4 separated subpages

16K bytes

Small Page

4K bytes

4 separated subpages

1K byte

Tiny Page

1K byte

Tiny Page

AT91SAM9G45-CU Datasheet(PDF) 44 Page - ATMEL Corporation

AT91SAM9G45-CU Datasheet(HTML) 44 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL