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HMF1M32F2VC Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd

Part # HMF1M32F2VC
Description  Flash-ROM Module 4MByte (1Mx32Bit), 80Pin-MMC, 3.3V Design
PDF  8 Pages
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Manufacturer  HANBIT [Hanbit Electronics Co.,Ltd]
Direct Link  http://www.hbe.co.kr
Logo HANBIT - Hanbit Electronics Co.,Ltd

HMF1M32F2VC Datasheet(HTML) 4 Page - Hanbit Electronics Co.,Ltd

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HANBit
HMF1M32F2VC
URL:www.hbe.co.kr
- 4 -
HANBit Electronics Co., Ltd.
REV.2.0 (October, 2002)
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
TYP.
MAX.
UNIT
COMMENTS
Sector Erase Time
-
0.7
15
sec
Chip Erase Time
25
sec
Excludes 00H programming
prior to erasure
Byte Programming Time
-
9
300
µs
Chip Programming Time
-
18
54
sec
Excludes system-level
overhead
TSOP CAPACITANCE
PARAMETER
SYMBOL
PARAMETER
DESCRIPTION
TEST SETUP
MIN
MAX
UNIT
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes : Test conditions TA = 25
o C, f=1.0 MHz.
AC CHARACTERISTICS
u Read Only Operations Characteristics
PARAMETER
SYMBOLS
Speed Options
JEDEC STANDARD
DESCRIPTION
TEST SETUP
-70R
-80
-90
-120
UNIT
tAVAV
tRC
Read Cycle Time
Min
70
80
90
120
ns
tAVQV
tACC
Address to Output Delay
/CE = VIL
/OE = VIL
Max
70
80
90
120
ns
tELQV
tCE
Chip Enable to Output Delay
/OE = VIL
Max
70
80
90
120
ns
tGLQV
tOE
Chip Enable to Output Delay
Max
30
30
35
35
ns
tEHQZ
tDF
Chip Enable to Output High-Z
Max
25
25
30
30
ns
tGHQZ
tDF
Output Enable to Output High-Z
Max
25
25
30
30
ns
tAXQX
tQH
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First
Min
0
ns
TEST SPECIFICATIONS
TEST CONDITION
70R, 80
90, 120
UNIT
Output load
1TTL gate
Output load capacitance,CL (Including jig capacitance)
30
100
pF
Input rise and full times
5
ns
Input pulse levels
0.0-3.0
V
Input timing measurement reference levels
1.5
V
Output timing measurement reference levels
1.5
V



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