ATtiny167-ESSZ datasheet(63/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

8.3

External Interrupts Register Description

8.3.1

External Interrupt Control Register A – EICRA

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bit 7..4 – Res: Reserved Bits

These bits are unused bits in the ATtiny87/167, and will always read as zero.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the

interrupt are defined in Table 8-1. The value on the INT1 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 8-1. The value on the INT0 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

8.3.2

External Interrupt Mask Register – EIMSK

• Bit 7, 2 – Res: Reserved Bits

These bits are unused bits in the ATtiny87/167, and will always read as zero.

Bit

654321

–

ISC11

ISC10

ISC01

ISC00

EICRA

Read/Write

R/W

Initial Value

000000

Table 8-1.

Interrupt Sense Control

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any logical change on INTn generates an interrupt request.

The falling edge of INTn generates an interrupt request.

The rising edge of INTn generates an interrupt request.

Bit

76543210

––––––

INT1

INT0

EIMSK

Read/Write

RRRRRR

R/W

Initial Value

00000000

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