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ATtiny167-ESSZ Datasheet(PDF) 253 Page - ATMEL Corporation |
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ATtiny167-ESSZ Datasheet(HTML) 253 Page - ATMEL Corporation |
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253 / 282 page  253 7728D–AVR–07/09 ATtiny87/ATtiny167 22.10 SPI Timing Characteristics See Figure 22-6 and Figure 22-7 for details. Note: In SPI Programming mode the minimum SCK high/low period is: - 2 t CLCL for fCK < 12 MHz - 3 tCLCL for fCK >12 MHz Figure 22-6. SPI Interface Timing Requirements (Master Mode) Table 22-12. SPI Timing Parameters Description Mode Min. Typ. Max. 1 SCK period Master See Table 13-4 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • t sck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • t ck 11 SCK high/low (1) Slave 2 • tck 12 Rise/Fall time Slave 1.6 µs 13 Setup Slave 10 ns 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 2 • t ck MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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