8

AT60142HT

7841A–AERO–10/09

Write Cycle 1.

WE Controlled, OE High During Write

Write Cycle 2.

WE Controlled, OE Low

Write Cycle 3.

CS Controlled

Note:

The internal write time of the memory is defined by the overlap of CS Low and W LOW.

Both signals must be activated to initiate a write and either signal can terminate a write

by going in active mode. The data input setup and hold timing should be referenced to

the active edge of the signal that terminates the write.

E

E

E