ATmega16A datasheet(126/352 Pages) ATMEL

126 / 352 page

126

8154B–AVR–07/09

ATmega16A

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of Period 2 in Figure 17-7 OCn has a transition from high to l ow even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that will give transition without Compare Match:

• OCR2A changes its value from Max, like in Figure 17-7. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must be correspond the the result of an

up-counting Compare Match.

• The Timer starts counting from a value higher than the one in OCR2A, and for that reason

misses the Compare Match and hence the OCn that would have happened on the way up.

17.8

Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk

T2)

is therefore shown as a clock enable signal. In Asynchronous mode, clk

I/O should be replaced by

the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are

set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 17-8. Timer/Counter Timing Diagram, no Prescaling

Figure 17-9 shows the same timing data, but with the prescaler enabled.

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

ATmega16A Datasheet(PDF) 126 Page - ATMEL Corporation