ATmega16A datasheet(124/352 Pages) ATMEL

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8154B–AVR–07/09

ATmega16A

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2 and TCNT2.

Figure 17-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Set-

ting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can

be generated by setting the COM21:0 to 3 (see Table 17-4 on page 132). The actual OC2 value

will only be visible on the port pin if the data direction for the port pin is set as output. The PWM

waveform is generated by setting (or clearing) the OC2 Register at the compare match between

OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the coun-

ter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be

a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a

constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform

generated will have a maximum frequency of f

oc2 = fclk_I/O/2 when OCR2 is set to zero. This fea-

ture is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output

compare unit is enabled in the fast PWM mode.

17.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

fOCnPWM

clk_I/O

N 256

⋅

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ATmega16A Datasheet(PDF) 124 Page - ATMEL Corporation

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