ATmega32A datasheet(77/352 Pages) ATMEL

77 / 352 page

8155B–AVR–07/09

ATmega32A

the OCR0 value, the compare match will be missed, resulting in incorrect waveform generation.

Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.

The setup of the OC0 should be performed before setting the Data Direction Register for the port

pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare

(FOC0) strobe bits in Normal mode. The OC0 Register keeps its value even when changing

between waveform generation modes.

Be aware that the COM0[1:0] bits are not double buffered together with the compare value.

Changing the COM0[1:0] bits will take effect immediately.

14.6

Compare Match Output Unit

The Compare Output mode (COM0[1:0]) bits have two functions. The Waveform Generator uses

the COM0[1:0] bits for defining the Output Compare (OC0) state at the next compare match.

Also, the COM0[1:0] bits control the OC0 pin output source. Figure 14-4 shows a simplified

schematic of the logic affected by the COM0[1:0] bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O port Control Registers

(DDR and PORT) that are affected by the COM0[1:0] bits are shown. When referring to the OC0

state, the reference is for the internal OC0 Register, not the OC0 pin. If a System Reset occur,

the OC0 Register is reset to “0”.

Figure 14-4. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0) from the Waveform

Generator if either of the COM0[1:0] bits are set. However, the OC0 pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

on the pin. The port override function is independent of the Waveform Generation mode.

The design of the output compare pin logic allows initialization of the OC0 state before the out-

put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 84.

PORT

DDR

OCn

Waveform

Generator

COMn1

COMn0

FOCn

clk

I/O

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