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ATmega1284P Datasheet(PDF) 92 Page - ATMEL Corporation |
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ATmega1284P Datasheet(HTML) 92 Page - ATMEL Corporation |
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92 / 468 page  92 8152G–AVR–11/09 ATmega164PA/324PA/644PA/1284P Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0(1) Signal Name PD3/INT1/TXD1/ PCINT27 PD2/INT0/RXD1/ PCINT26 PD1/TXD0/ PCINT25 PD0/RXD0/ PCINT27 PUOE TXEN1 RXEN1 TXEN0 RXEN1 PUOV 0 PORTD2 • PUD 0PORTD0 • PUD DDOE TXEN1 RXEN1 TXEN0 RXEN1 DDOV 1 0 1 0 PVOE TXEN1 0 TXEN0 0 PVOV TXD1 0 TXD0 0 DIEOE INT1 ENABLE PCINT27 • PCIE3 INT2 ENABLE PCINT26 • PCIE3 PCINT25 • PCIE3 PCINT24 • PCIE3 DIEOV 111 1 DI INT1 INPUT PCINT27 INPUT INT0 INPUT RXD1 PCINT26 INPUT PCINT25 INPUT RXD0 PCINT24 INPUT AIO ––– – |
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