ATmega64A datasheet(107/392 Pages) ATMEL

107 / 392 page

107

8160C–AVR–07/09

ATmega64A

When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0

bit setting. Table 14-3 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a

Normal or CTC mode (non-PWM).

Table 14-4 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare

Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 98

for more details.

Table 14-5 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase cor-

rect PWM mode.

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare

Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

100 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table

14-6.

Table 14-3.

Compare Output Mode, non-PWM Mode

COM01

COM00

Description

Normal port operation, OC0 disconnected.

Toggle OC0 on Compare Match.

Clear OC0 on Compare Match.

Set OC0 on Compare Match.

Table 14-4.

Compare Output Mode, Fast PWM Mode

(1)

COM01

COM00

Description

Normal port operation, OC0 disconnected.

Reserved

Clear OC0 on Compare Match, set OC0 at BOTTOM,

(non-inverting mode).

Set OC0 on Compare Match, clear OC0 at BOTTOM,

(inverting mode).

Table 14-5.

Compare Output Mode, Phase Correct PWM Mode

(1)

COM01

COM00

Description

Normal port operation, OC0 disconnected.

Reserved.

Clear OC0 on Compare Match when up-counting. Set OC0 on Compare Match

when downcounting.

Set OC0 on Compare Match when up-counting. Clear OC0 on Compare Match

when downcounting.

ATmega64A Datasheet(PDF) 107 Page - ATMEL Corporation

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