ATmega64A datasheet(109/392 Pages) ATMEL

109 / 392 page

109

8160C–AVR–07/09

ATmega64A

• Bit 2 – TCN0UB: Timer/Counter0 Update Busy

When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.

When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.

• Bit 1 – OCR0UB: Output Compare Register0 Update Busy

When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set.

When OCR0 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.

• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy

When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set.

When TCCR0 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value.

If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0,

the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary stor-

age register is read.

14.11.5

TIMSK – Timer/Counter Interrupt Mask Register

• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt

Flag Register – TIFR.

14.11.6

TIFR – Timer/Counter Interrupt Flag Register

• Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0 and the

data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to

Bit

65432

0x37 (0x57)

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

TIMSK

Read/Write

R/WR/W

Initial Value

00000

Bit

765

43210

0x36 (0x56)

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

TIFR

Read/Write

R/W

Initial Value

000

00000

ATmega64A Datasheet(PDF) 109 Page - ATMEL Corporation

ATmega64A Datasheet(HTML) 109 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL