ATmega64A datasheet(229/392 Pages) ATMEL

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229

8160C–AVR–07/09

ATmega64A

• Bits 7:0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the Two-wire Serial Bus.

21.9.5

TWAR – TWI (Slave) Address Register

The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of

TWAR) to which the TWI will respond when programmed as a slave transmitter or Receiver, and

not needed in the Master modes. In multimaster systems, TWAR must be set in masters which

can be addressed as slaves by other masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an

associated address comparator that looks for the slave address (or general call address if

enabled) in the received serial address. If a match is found, an interrupt request is generated.

• Bits 7:1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.

Bit

6543

(0x72)

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

TWAR

Read/Write

R/W

Initial Value

1111

ATmega64A Datasheet(PDF) 229 Page - ATMEL Corporation