APL5156 datasheet(9/18 Pages) ANPEC

9 / 18 page

Rev. A.6 - Oct., 2009

APL5156

www.anpec.com.tw

where T

J-TA is the temperature difference between the

junction and ambient air.

JA is the thermal resistance

between junction and ambient air.

For continual operation, do not exceed the absolute maxi-

mum junction temperature rating of T

J=125

For example:

In SOT-23-5 package

JA=235

C/W. When operates the

APL5156 at T

A=50

C, the maximum power dissipation

can be determined as below:

Application Information

Thermal Pad Consideration

)

MAX

(

−

D(MAX)=(125

C-50

C)/(235

C/W)

D(MAX)=319.1mW

Enable/Shutdown

The APL5156 features an active-high enable pin that al-

lows the regulator to be disabled. Forcing the enable pin

low disables the regulator, so current consumed by the

regulator goes nearly to zero. Forcing the enable pin high

enables the output voltage. The enable pin can not float.

Input Capacitor

The APL5156 has high input voltage up to 25V. The input

capacitor must be rated to sustain voltages that may be

used on the input. An input capacitor may be required

when the device is not near the source power supply or

when supplied by a battery. Small and surface-mounted

ceramic capacitors can be used for bypassing. A larger

value may be required if the source supply has high ripple.

Output Capacitor

The APL5156 requires an output capacitor for stability.

The design requires 2.2

µF or greater on the output to

maintain stability. It is optimized by using low-ESR ce-

ramic chip capacitors. The maximum allowable ESR is

Ω. More capacitance improves transient response. Place

the output capacitor as close to the VOUT pin as possible.

X7R/X5R dielectric-type ceramic capacitors are recom-

mended because of their temperature performance. X7R

type capacitors change capacitance by 15% over their

operating temperature ranges. To use a ceramic chip

capacitor with Y5V dielectric, the value must be much

higher than an X7R ceramic capacitor to ensure the same

minimum capacitance over the equivalent operating tem-

perature range.

No-Load Stability

The APL5156 will remain stable and in regulation with no

load unlike many other voltage regulators. This is espe-

cially important in CMOS RAM keep-alive applications.

Thermal Consideration

The thermal resistance of junction to ambient controls

the APL5156's maximum power dissipation. The power

dissipation across the device is P

D=IOUT (VIN-VOUT), and the

maximum power dissipation is:

The SOP-8P is a cost-effective package which features a

small size, like a standard SOP-8, and a bottom thermal

pad to minimize the thermal resistance of the package is

applicable to high current applications. The thermal pad

must be soldered down to the copper plane on circuit

board. Heat can be conducted away from the thermal

pad through the copper plane to ambient. If the copper

plane is not on the top surface of the circuit board, 4 or 6

vias should be used to thermally couple the thermal pad

to the bottom plane.

For good thermal conduction, the vias must be plated

through and solder filled. The copper plane used to con-

duct heat away from the thermal pad should be as large

as practical.

SOP-8P Layout Recommendation

0.150

0.072

0.212

0.118

ground

plane for

thermal

pad

0.024

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