33899 datasheet(15/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33899

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Figure 9. Re-enable after a Low Side Current Comparator Trip

LOW SIDE CURRENT COMPARATOR VS.

CURRENT LIMIT LEVELS

There are two different current limit thresholds for the low

side MOSFETs: current comparator and current limit. Current

comparator is the normal commanded switching current.

Current limit is for fault protection.

The inductance of the load results in just the current

comparator tripping. Once the low side current comparator

has tripped and filter time expired, the low side MOSFET

turns off and the high side MOSFET subsequently turns on

for normal current re-circulation in the load. If an actual hard

short to either VIGNP or ground on the S0/S1 outputs is

encountered, the current limit kicks in and prevents large

current spikes from VIGNP (or to ground) to occur. The

threshold level of the current comparator vs. the high and low

side current limits is given in the Static Electrical

Characteristics table, page 8.

As backup protection, there is a linear overcurrent

controller to limit current spikes during timer operations.

SERIAL PERIPHERAL INTERFACE (SPI)

The 33899 has a serial peripheral interface consisting of

Chip Select (CS), Serial Clock (SCLK), Serial Data Out (DO),

and Serial Data In (DI). This device is configured as a SPI

slave and is daisy-chainable (single CS for multiple SPI

slaves).

CHIP SELECT (CS)

The CS is a low = true input that selects this device for

serial transfers. On the falling edge of CS, the DO pin is

released from tri-state mode, and all status information is

latched in the SPI shift register. While CS is asserted, register

data is shifted into the DI pin and shifted out of the DO pin on

each subsequent SCLK. On the rising edge of CS, the DO pin

is placed in a high-impedance state and the Fault register

reloaded (latched) with the current filtered status data. To

allow sufficient time to reload the Fault register, the CS pin

must remain low for a minimum of tCSN prior to going high

again.

By design, the CS input is immune to spurious pulses of

50 ns or shorter. (DO may come out of tri-state, but no status

bits are cleared and no control bits are changed.)

The CS input has a 50

μA current source to VCC, which

pulls this pin to VCC if an open circuit condition occurs. This

pin has TTL-level compatible input voltages, which allows

proper operation with microprocessors using a 3.0V to 5.0V

supply.

SERIAL CLOCK (SCLK)

The SCLK input is the clock signal input for

synchronization of serial data transfer. This pin has TTL-level

compatible input voltages, which allow proper operation with

microprocessors using a 3.3V to 5.0V supply.

When CS is asserted, both the microprocessor and the

33899 latch input data on the rising edge of SCLK. The SPI

master typically shifts data out on the falling edge of SCLK,

while the 33899 shifts data out on the falling edge of SCLK to

allow more time to drive the DO pin to the proper level.

SERIAL DATA OUTPUT (DO)

The DO is the SPI data out pin. When CS is asserted (low),

the MSB is the first bit of the word transmitted on DO and the

LSB is the last bit of the word transmitted on DO. After all 8

bits of the fault register are transmitted, the DO output

sequentially transmits the digital data that was just received

on the DI pin. This allows the processor to distinguish a

shorted DI pin condition. The DO output continues to transmit

LS Current Comparator

PWM

REDIS

4 VDC

Iload

Reset to

0 VDC

Reset to

0 VDC

t = 33.3 * C (nF)

μs

tmin = 25μs

t = 33.3 * C (nF)

μs

tmin = 25μs

33899 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

33899 Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc

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