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34845 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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34845 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 21 page ![]() Analog Integrated Circuit Device Data 4 Freescale Semiconductor 34845 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Maximum Pin Voltages SWA, SWB, VOUT CH1, CH2, CH3, CH4, CH5, CH6 (Off state) CH1, CH2, CH3, CH4, CH5, CH6 (On state) FAIL, OVP COMP, ISET PWM, WAKE EN, VIN VMAX -0.3 to 65 -0.3 to 45 -0.3 to 20 -0.3 to 7.0 -0.3 to 2.7 -0.3 to 5.5 -0.3 to 24 V Maximum LED Current per Channel ILED_MAX 33 mA ESD Voltage(1) Human Body Model (HBM) Machine Model (MM) VESD ±2000 ±200 V THERMAL RATINGS Operating Ambient Temperature Range TA -40 to 85 °C Maximum Junction Temperature TJ 150 °C Storage Temperature Range TS -40 to 150 °C Peak Package Reflow Temperature During Reflow(2), (3) TPPRT Note 3 °C Thermal Resistance Junction to Ambient(4) TθJA 36 °C/W Thermal Resistance Junction to Case(5) TθJC 3.1 °C/W Power Dissipation(4) TA = 25°C TA = 85°C PD 3.4 1.8 W Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2) (CZAP = 100 pF, RZAP = 1500 Ω), and the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω. 2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 4. Per JEDEC51-8 Standard for Multilayer PCB 5. Theoretical thermal resistance is from the die junction to the exposed pad. |
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